The stock’s recent volatility has been driven by two overlapping factors: reports that some OpenAI Ultrafast workloads moved to Nvidia GPUs, and the staggered post-IPO lockup schedule that continues to release shares. Neither issue has invalidated the core contract, but both have tested investor confidence in the near term.

The Technology Edge: Wafer-Scale for Inference

Cerebras’s core product is the Wafer-Scale Engine. Rather than cutting a silicon wafer into hundreds of individual dies, the company uses the entire wafer as a single processor. The current WSE-3 generation contains roughly 4 trillion transistors and 900,000 cores, with approximately 44 GB of on-wafer SRAM.

This architecture addresses a fundamental bottleneck in inference. Generating tokens is primarily a memory-bandwidth problem. On conventional GPUs, model weights reside in HBM and must be streamed to the compute units for every token. Cerebras places a large portion of the model weights directly on the wafer, eliminating most of that trip. The company claims aggregate memory bandwidth on the order of 21 PB/s — orders of magnitude higher than an H100.

The practical result has been measurable speed advantages on hosted inference. Cerebras has demonstrated multi-thousand tokens per second on various open models, and OpenAI previously used the platform for an Ultrafast tier of GPT-5.6 Sol at roughly 750 tokens per second. Newer systems such as the CS-4 (three WSE-3 Turbo wafers per rack) claim further gains in tokens-per-second-per-user and efficiency.

One under-appreciated detail in the CS-4 design is the power delivery path. In a conventional system the distance from the voltage regulators to the compute die is often on the order of 50 mm. Cerebras packs conversion, liquid cooling, and I/O into a pluggable “backpack” that sits directly against the wafer, reducing that gap to roughly 0.5 mm. The shorter path cuts impedance and enables the higher clocks on the WSE-3 Turbo. It is a small mechanical change with a large electrical consequence — the kind of systems-level optimization that is easy to overlook when the conversation stays at the level of “wafer versus GPU.”

The company has also announced disaggregated inference architectures with AMD (Helios for prefill, Cerebras for decode) targeting higher tokens per second per watt, and a similar approach with AWS Trainium for Bedrock.

The advantage is clearest for latency-sensitive, interactive, or agentic workloads where tokens-per-second-per-user matters more than raw throughput per dollar. It is less relevant for high-concurrency batch inference or training. Cerebras is not trying to replace Nvidia across the entire stack; it is arguing for a specialized role in the decode phase and for workloads that value speed. That distinction has been consistent in primary statements from both Cerebras and OpenAI, even as third-party reporting has focused on individual model launches running elsewhere.

The OpenAI Master Relationship Agreement

In December 2025 Cerebras signed a Master Relationship Agreement with OpenAI. Under the agreement OpenAI committed to purchase 750 MW of AI inference capacity, delivered in three 250 MW segments:

• 250 MW by the end of 2026

• Additional 250 MW by the end of 2027 (cumulative 500 MW)

• Additional 250 MW by the end of 2028 (cumulative 750 MW)

OpenAI also holds an option, not a commitment, for an additional 1.25 GW by the end of 2030. Cerebras has valued the committed portion at more than $20 billion. OpenAI provided an approximately $1 billion secured working-capital loan (partly repayable via service credits) and received warrants tied to milestones, including capacity delivery.

Remaining Performance Obligations stood at $25.4 billion as of June 30, 2026. Management has stated that a significant portion is attributable to the OpenAI agreement. Recognition is deliberately back-loaded: the company expects only about 22% (roughly $5.6 billion) to be recognized in the 24 months ending June 30, 2028, with another 43% in the subsequent 24 months. In Q2 2026 Cerebras recognized approximately $56.8 million of revenue under the arrangement, equal to roughly 32% of GAAP revenue.

The contract does not prevent OpenAI from using other hardware for specific tiers or models. Reports that a newer Ultrafast offering ran on Nvidia GPUs therefore do not cancel the 750 MW commitment. They do, however, reduce the probability that the 1.25 GW option will be exercised and weaken the narrative that Cerebras exclusively powers OpenAI’s fastest service. Sam Altman’s subsequent statement that Cerebras is a “close partner” provided some reassurance on the committed capacity.

Importantly, management has noted that the $25.4 billion RPO figure does not currently include material backlog from AWS or other hyperscalers. Any AWS Bedrock contribution would be incremental.

Financial Snapshot and Margin Path

Q2 2026 results (August 12) showed:

• Core (non-GAAP) revenue of $209.9 million, up 103% year-over-year

• Core cloud and other services revenue of $127.7 million, up 287%

• Core gross margin of approximately 40.6–41%

• Core operating margin of –16% (improved by roughly 2,600 basis points year-over-year)

• GAAP revenue of $180.1 million (the difference largely reflects customer-warrant amortization and pass-through data-center costs)

Management raised full-year 2026 core revenue guidance to $880–890 million and core gross margin guidance to 41–43%. Core operating margin guidance for the year is –19% to –17%. The company has stated it expects core revenue to more than triple in 2027. UBS has published a more aggressive path: roughly $890 million in FY26E, $3.3 billion in FY27E, and approximately $22.6 billion in FY30E with a 46% EBIT margin. Consensus estimates are somewhat more conservative but still imply more than a tripling of revenue by 2027.

Near-term GAAP gross margins are depressed by leaseback arrangements (Cerebras has rented back some of its own systems to meet demand while owned capacity is built) and by warrant amortization. Core margins, which exclude these items, are the metric management emphasizes. The path to the longer-term 40%+ core operating margin target depends on shifting from higher-cost rented capacity to owned data centers and on improved utilization and pricing.

Capacity Buildout

Cerebras has stated that more than 600 MW of data-center capacity is live or under contract for delivery by the end of 2027. Manufacturing capacity is expected to scale more than 10× in 2026, with additional lines at Flex, Sanmina, and Rocket EMS, and secured TSMC wafer supply. European capacity is targeted at roughly 200 MW by the end of 2027 (France and the Nordics), including a phased 165 MW project in Mikkeli, Finland. The company has also referenced a gigawatt-scale pipeline of potential sites.

The OpenAI deployment schedule requires capacity to come online in stages through 2028. Delays in site selection, power interconnection, or construction could affect revenue recognition timing and, in extreme cases, trigger contractual remedies. Management has acknowledged the need to accelerate data-center buildout.

Partnerships and Diversification Efforts

Beyond OpenAI, Cerebras has announced:

• An AWS collaboration pairing Trainium (prefill) with Cerebras (decode), targeted for Amazon Bedrock in Q1 2027

• An AMD partnership for a disaggregated Helios + Wafer-Scale Engine solution, expected in production on Cerebras Cloud in Q4 2026, with claimed efficiency gains

• A CrowdStrike partnership under which Falcon AI Detection and Response models run on Cerebras hardware; Cerebras also standardizes on Falcon for its own security

• Other named customers or users including Cognition, Lovable, Block, Figma, AlphaSense, GSK, and various open-model hosts

These relationships broaden the addressable use cases (coding agents, cybersecurity, enterprise inference) and reduce, over time, the percentage of revenue coming from any single customer. OpenAI is still expected to remain meaningful in 2027.

Lockup Schedule and Insider Selling

Cerebras structured its lockup as a staggered release rather than a single expiration date. Smaller tranches of approximately 14.6 million shares were released biweekly starting in mid-August. Larger tranches of up to 19.4 million shares were scheduled for September 30, October 14, and October 28. The final lockup expires on the earlier of the second trading day after third-quarter results or November 9, 2026. In total, an estimated 171 million shares are subject to early release under the published schedule.

“Up to” means the figure is a ceiling; not every eligible share will be sold. Still, prior unlock dates have coincided with price declines. Separately, insiders have sold substantial amounts under 10b5-1 plans. CEO Andrew Feldman and CTO Sean Lie sold more than $240 million of Class A shares between late August and late September. The COO sold roughly $81 million around the end of September. Cumulative insider sales since the IPO run into the hundreds of millions of dollars. Most were planned, but the volume contributes to supply overhang perceptions.

Valuation Context and Risks

At roughly $35 billion market cap and ~$890 million of 2026 core revenue guidance, the stock trades at a high multiple of near-term sales. The multiple compresses rapidly if 2027 revenue approaches the $3 billion range and continues to scale. The company still reports significant GAAP losses, and free cash flow is negative while capital is deployed into data centers. Customer concentration, execution risk on the multi-year buildout, and competition from Nvidia (and specialized inference players such as Groq) remain the primary risks. The 1.25 GW option is not contracted revenue and should not be treated as such.

Key Watch Items

• Q3 2026 results and whether core revenue and margin guidance are met

• Progress on the 2026 OpenAI capacity tranche and overall data-center deliveries

• Any clarification on OpenAI Ultrafast hardware mix or option exercise signals

• Further lockup-related supply and insider activity through late October and early November

• Evidence of customer diversification and contribution from AWS, AMD, or security workloads

• Transition from rented to owned capacity and its impact on core margins

Cerebras has a differentiated architecture that is well suited to a growing class of latency-sensitive inference workloads, a large contracted backlog anchored by OpenAI, and the cash raised in its IPO to fund expansion. Converting that backlog into recognized, high-margin revenue on schedule, while reducing customer concentration and navigating ongoing share supply, is the multi-year test that will determine whether the current valuation is attractive or still demanding.

I first wrote that on 2 August, as an X Article, after dinner with a Qorvo engineer who said the name would disappear sooner than most people expected. Inside the company the rumor was already specific. An IT colleague had a date he had to be back from a trip. Some people treated that date as the last day of @qorvo.com. I do not know if the date was real. The fact that people were trading it was the story. They could already feel the end.

Six weeks later the calendar caught up with the rumor.

In October 2025 Skyworks and Qorvo announced a cash-and-stock merger valued at about $22 billion. Shareholders of both companies approved the deal on 11 February 2026. The U.S. antitrust wait is over. What remains, management keeps naming in public, is China’s SAMR review. At a Goldman conference last week Skyworks CEO Phil Brace said he was very confident the deal closes this calendar year, and that the company is preparing to close this fiscal year — Skyworks’ year ends 2 October. He put the image on the record: around the airport, waiting for permission to land.

Once it lands, Qorvo stops being an independent public company. The stock delists. The email domains change. The separate name fades into Skyworks.

The parts do not.

Two suppliers, one socket fight

For years Skyworks and Qorvo were the two large RF front-end houses selling into the same phones. Power amplifiers, filters, switches, antenna tuners, modules. They fought for sockets in iPhones and Galaxy phones. Apple in particular got what a buyer wants from that structure: two independent sources that could not treat a design-win as a permanent rent.

The same rivalry ran at Samsung. Qorvo kept a real position there — power amplifiers, filters, antenna tuning, Wi-Fi, ultra-wideband — with Samsung in the low teens of Qorvo revenue in recent years. Skyworks sold Samsung too, more selectively, on the high-performance side. In 2024 the two companies even announced a collaboration to put Skyworks’ SKY5 front-end into Samsung’s next 5G modem platforms. They were already acting like one supply base before the lawyers finished the merger.

That is the part of this deal that matters on a phone board. Two names that used to bid against each other will, after close, answer to one P&L.

RFMD, TriQuint, then Qorvo

This is not Qorvo’s first renaming.

Qorvo was created on 1 January 2015 by the merger of RF Micro Devices and TriQuint Semiconductor.

RFMD was founded in 1991 in Greensboro, North Carolina, by three former Analog Devices engineers — William Pratt, Powell Seymour, and Jerry Neal. The company was built for commercial wireless, and for gallium arsenide HBT power amplifiers in handsets. By the late 1990s and 2000s it was one of the names you saw on the PA in a phone.

TriQuint is older. It spun out of Tektronix in Oregon in 1985. The name is a periodic-table joke: tri for group III, quint for group V — gallium arsenide. Early work was high-speed GaAs digital and analog. In 1991 it absorbed Gazelle Microcircuits and Gigabit Logic and pulled several of the early GaAs groups under one roof.

The 2015 combination took the Qorvo name and put headquarters in Greensboro. The portfolio got wider than handsets: infrastructure, defense, later IoT and power. For a little more than a decade Qorvo was the independent RF house that name referred to.

The same pressure, one more time

The forces that made RFMD and TriQuint into Qorvo are the forces making Qorvo into Skyworks. Scale. Customer concentration, especially Apple. The cost of staying in advanced filters, modules, and compound semiconductors when the customer list does not get longer.

If Brace’s calendar holds, the Qorvo name starts its formal retirement in the coming weeks, not the coming years. Business cards, badge systems, email, the ticker. Another familiar RF brand becomes a line in a corporate history.

RFMD became Qorvo. Qorvo is becoming part of Skyworks. Two suppliers that spent a decade competing at Apple and Samsung will operate as one.

The technology continues. The names usually do not.

This first ran as an X Article on 2 August 2026. The close window is what changed.

I first used an Arm core in 1998. The constraint then was megahertz versus milliamps.

What Arm announced on 8 September as CSS for Mobile 2 is not a faster Cortex with a new letter. It is Arm saying, in product form, that an on-phone agent is not an NPU inference job. Speech, retrieval, reason, app launch, browse, action — that loop has to close inside a thermal box. The CPU is the orchestration engine. The GPU owns pixels, including the new neural ones. There is no NPU in the CSS. A partner who wants one attaches it. The interconnect is what keeps the 24 percent end-to-end number from falling apart.

Cortex did not vanish. The label did.

Most people still say Cortex-X and Cortex-A. That is the last generation that used those names in a mobile CSS. In 2025 Arm stopped putting Cortex on new application cores and started counting C1, C2. The ISA did not change families. Armv9-A is still Armv9-A. What changed is the product label, and the cluster grew a fourth tier.

The map, in the language you already have:

Premium is not A725 with a new badge. It is a shaved Ultra — same class of pipeline, less area. Three layers became four. C2 is the next microarchitecture on that four-layer map, not a new ISA and not the same silicon as a C1 phone already in a pocket.

Today’s CSS for Mobile 2 cluster, as Arm drew it, is C2-Ultra + C2-Pro + two SME2 (Scalable Matrix Extension 2) units. That is why the rest of this piece talks Ultra and Pro, not X and A7.

Cortex-M and Cortex-R did not move into this letter. An M85 is still an M85. Different profile, different article.

A CSS is a floor you can close. A core is not.

A core drop is an RTL view and a TRM. You take the core, you wrap a bus, you give it an interrupt map, you close timing against a memory system you designed yourself. That is a real job. It is also how a phone SoC used to eat a year after the ISA slide.

CSS — Compute SubSystem — is Arm selling the next layer up. CSS for Mobile 2 packages the C2 cluster, Mali G2-Ultra NX, the SI L2 interconnect (system interconnect — not CPU L2), a physical implementation, and a software reference: KleidiAI, the Neural Graphics Development Kit, AI Portal, MCP Server.

Physical implementation is the part most write-ups skip, and it is the part a back-end person actually buys. Arm is not handing you the GDS of a finished phone. It is handing you a timing-closed starting point: compiled memories, a clock and power grid that already survived a target process, isolation cells and RAM compilers you do not have to rediscover on the first place-and-route pass. Partners still own the modem, the ISP, the NPU if any, the DRAM PHY, and the skin. They can take the pieces independently or mix them with their own IP and third-party blocks.

That last sentence is the product. A CSS is a coherency story and a schedule story. It is not a locked SoC, and it is not “the next phone is an Arm reference design.”

The floor is drawn for a workload Arm is now calling agentic. The word is tired. The job is not. An agent does not emit a token and stop. It keeps task state. It decides where the next stage runs — a local model on SME2, a local app, a partner accelerator, or the network — and it comes back. Repeatedly. Under the same skin temperature you already know from flagship phones.

That is why the old scoreboard splits, and why a bigger core is the wrong unit of progress.

Single-thread latency still matters because the decisions are serial. Permission check. Tool pick. “Open this app.” Those do not parallelize. Multi-thread matters because retrieval, model prep, and the compositor do not wait for each other. Memory movement matters because none of those stages live in one SRAM. If you only ship a wider Ultra, you win the SPECint slide and lose the loop.

The C2 cluster: two kinds of CPU, and a matrix floor that is not a core

The cluster Arm is selling is C2-Ultra plus C2-Pro plus two SME2 units. Arm did not publish core counts, L2/L3 sizes, or the exact socket the matrix units sit in. I will not invent them. What is stated, and what a cluster person can still read, is the split of labor.

Read more

A week after Hot Chips, the argument on X split into two questions that should never have been fused. Is the architecture garbage? And can this company be worth the multiple the tape is using?

The hallway version was cruder. Cerebras put Rubin in an adjacent column, talked about stitching wafers together, and put stacked DRAM on a roadmap slide. OpenAI showed Jalapeño. Nvidia showed a Groq-class LPX rack. The reconstruction that followed was tidy, and wrong in one direction, and right in another:

The wafer that was supposed to do everything now needs friends. Therefore the idea failed.

What ended is a pitch. The pitch was: one wafer, weights resident, no off-chip, no DRAM, no cluster politics. That sentence was already under stress when I read the S-1 in May. Hot Chips made the stress official.

What did not fail is the physical fact that still distinguishes the part. Almost a million small cores, each with its own SRAM, talking to neighbors in a single-cycle mesh on 46,225 mm² of silicon. That locality is real. It is also smaller than the models people now want to serve. The rest of this piece is about that gap — how Cerebras discovered it in public, and what it is building instead of pretending the gap is not there.

Three documents, three questions

I did not come to this company this week.

The first document is the S-1 I read while submitting an indication of interest on SoFi, because Robinhood did not have the deal. That filing answers a manufacturing question: how do you ship a chip the size of a dinner plate?

The second is Supernova, 18 August, Sean Lie on stage with CS-4. That event answers a product question: what do you sell when the dinner plate is no longer large enough?

The third is Hot Chips, late August, same machine, different room. That talk answers a peer question, and answers it badly in places: where does this sit next to Rubin, LPX, Jalapeño, and a memory industry that is stacking DRAM onto logic?

Read separately, each document sounds like a win. Read in order, they are a narrowing.

What the S-1 actually invented

The invention was never “the largest chip.” Large is the result. The inventions are the things that keep a wafer alive after the foundry has done what foundries do — print defects into 46,225 mm² of N5.

Scribe-line stitching. A normal 300 mm wafer is a 12×7 grid of reticles that will be sawed apart. Cerebras does not saw. An offset exposure of upper metal uses the scribe lanes as wires and ties the reticles into one mesh. No active devices live in that stitch. The stitch is only interconnect, which is why a defect there can be repaired with a spare link instead of killing the wafer.

Harvest, not purity. Each core is about 0.05 mm². On a conventional reticle-sized SoC, a particle in the wrong place scraps the die — or at least a large block — because the functions on that die are not interchangeable. The WSE is populated with about 970,000 identical cores and ships with about 900,000 enabled. The same particle retires a tile. The mesh routes around it. Cerebras quotes this as ~93% silicon utilization. That is not foundry die-sort yield. Friends who have worked yield will tell you the same thing. Utilization after harvest and a wafer-sort pass rate are different meters. Confusing them is how the sentence “their yields suck” gets written by people who are not wrong about margins and are wrong about topology.

A five-port mesh. Tile = core + local SRAM + router. Four cardinal ports and one port into the core. Lossless flow control, single-cycle neighbor hops. Die-to-die is a short, source-synchronous, high-metal bus with redundant lanes and a state machine that fails over. Across a wafer the stitch count is large enough that defects in the interface are assumed.

MemoryX and SwarmX. This is the part of the S-1 that aged. The cluster language in the filing is still a training language. MemoryX parks weights off-wafer and streams a layer at a time. SwarmX is a data-parallel fabric for broadcast and reduction, drawn up to 2,048 nodes. That architecture can train a model whose weights will never fit in 44 GB. It also throws away the only number that made the wafer special. On-wafer SRAM moves at 21 PB/s. Off-wafer I/O on a CS-3 is about 150 GB/s. Stream the model and the dinner plate becomes an expensive socket.

I wrote the first version of this in May, after the S-1, before the stock had a ticker that anyone could fight about:

Cerebras solved two fundamental constraints in semiconductors at the same time: die size limit + off-chip memory bottleneck. The WSE-3 turns an entire 300mm wafer into one monolithic chip, completely eliminates HBM, and packs 44GB of distributed on-chip SRAM… 21 PB/s.
— 12 May 2026

That paragraph is still the right description of one wafer doing what fits on one wafer. It is no longer a description of the product Cerebras is shipping into 2027.

The first reaction was the correct engineering reaction

I have designed on nodes down to 2 nm. The first time someone described a 46,225 mm² processor to me, I said what every serious designer says.

Yield will be catastrophic. You cannot test it. You cannot route around that many defects.

Then the topology flips. Tiny identical cores. A reserve of about one percent. A mesh that treats a dead tile the way a datacenter treats a dead server. Weights that never leave SRAM if you keep the working set on the wafer. The sentence changes from insane to of course — not because the problems vanished, but because they were moved from process control to architecture.

I have had that conversation over dinner and on after-lunch walks more times than I can count. Ten minutes of the harvest story and the room changes register. That is why I was in the IPO. It is also why I added in the 401(k) after the IPO, the same way the Korean National Pension did. The technology was never the open question for me. The open question, which I wrote months ago and which the tape is still asking, was whether this thing earns money.

As a chip designer who has spent nearly three decades in Non-memory SoC, I still remember the exact second I first heard about Cerebras… “That’s insane. Yield will be catastrophic.” Then I studied the actual architecture… Suddenly the “insane” idea flipped into pure, shocking genius.
The technology was never the open question for me. The open question was always… “Earning money is the next problem with this amazing technology.”
— 17 August 2026

Hot Chips did not reopen the yield argument. It reopened the slogan.

From here the piece is for paid subscribers. Part 2 after the visit will live in the same post.

Read more

Executive Summary

The dominant narrative across the AI hardware ecosystem over the past two years has been remarkably singular: pure-play silicon designers—most notably NVIDIA—monopolize economic rent, while system-level Original Equipment Manufacturers (OEMs) operate as low-margin assemblers passing capital directly upstream.

Dell Technologies’ fiscal Q2 earnings report thoroughly dismantles this view. Delivering $47.0 billion in total net revenue (+58% YoY), $16.4 billion in AI-optimized server revenue, and an unprecedented $95.0 billion AI server backlog, Dell’s Infrastructure Solutions Group (ISG) expanded operating margins to 15.0% ($4.8 billion in segment operating income, up 225% YoY).

This performance, paired with a full-year revenue guidance increase of $25 billion to $192.0 billion, signals a structural transition in the market: as GPU compute scaling runs into acute memory and thermal boundaries, system-level architecture, enterprise integration, and supply-chain tollbooths dictate the pace of AI deployment.

1. TECH: The Infrastructure Triad—Memory, Liquid Cooling, and Storage Pull-Through

Raw floating-point operations per second (FLOPS) on an accelerator die are functionally useless without a balanced systems architecture. Dell’s Q2 results highlight three technical gating factors redefining OEM value capture:

Tech Gating Factor 1: The Memory Wall

While market attention remains focused on GPU availability, Dell management explicitly cited component supply shortages in DRAM and NAND memory as the primary bottleneck restricting immediate fulfillment.

When training large language models (LLMs) or executing multi-tenant inference workloads, GPU cores face severe pipeline stalls if memory bandwidth and capacity lag. System integration requires balancing high-bandwidth memory (HBM) on the accelerator with massive DDR5 main memory pools and enterprise ultra-low latency flash storage tiers to prevent memory starve conditions.

Tech Gating Factor 2: Thermal Physics and Liquid Cooling

As rack power densities exceed 100kW per cabinet, traditional air cooling reaches physical limits. Direct-to-Chip (D2C) liquid cooling, coolant distribution units (CDUs), and custom manifold engineering move system assembly from standard sheet-metal racking into precision liquid-flow engineering.

OEMs that engineer custom, thermally-optimized racks remove the deployment burden from enterprise data centers that lack specialized fluid-dynamics capabilities.

Tech Gating Factor 3: The System Pull-Through Effect

Deploying AI server racks creates a structural pull-through effect across enterprise infrastructure:

• Traditional Servers & Networking: Grew 122% YoY to $10.5 billion. High-throughput AI clusters require dedicated ingress/egress control-plane nodes and high-speed switching fabrics to handle telemetry and job orchestration.

• Enterprise Storage: Grew 26% YoY to $4.9 billion. Model checkpointing, vector database ingestion, and unstructured data indexing demand parallel file systems and high-IOPS IP storage arrays directly adjacent to compute clusters.

2. CAPITAL: Operating Margin Expansion and Political Portfolio Allocations

The market thesis that system integrators operate on pass-through economics is countered by Dell’s underlying cash generation and margin expansion.

Operating Leverage: Complexity Expands Margins

ISG operating income surged 225% YoY to $4.8 billion, driving segment operating margins to 15.0%. This margin expansion confirms that custom liquid-cooling configurations, integrated networking, and storage attachments allow OEMs to capture gross profit dollars far above base component costs.

Political Catalysts & Sovereign Capital Allocations

Public financial disclosures show Donald Trump’s personal portfolio acquired between $1 million and $5 million in Dell stock, closely preceding public remarks urging institutional and federal entities to “Trump Said “Go Buy a Dell” — But the Market Bought the AI Server Story”. This was shortly followed by landmark federal allocations, including a $9.7 billion U.S. Department of Defense enterprise contract.

Sovereign entities and federal defense agencies require secure, supply-chain-audited domestic system integrators capable of delivering air-gapped, turn-key AI hardware. Capital flows into domestic OEMs reflect their strategic role in securing national sovereign compute capacity.

3. EXECUTION: The Enterprise Shift from Hyperscale to Production

The first phase of the AI cycle was driven primarily by hyper-scaler capital expenditure for foundation model training. The secondary phase—deploying fine-tuned models and inference workloads inside global enterprise networks—presents a different execution challenge.

• Expanding Enterprise Base: Dell added 3,300 new AI customers over the last three quarters, bringing its total enterprise AI customer count past 6,500.

• Turnkey Infrastructure Requirements: Unlike hyper-scalers that build proprietary software stacks, enterprise clients require turnkey hardware solutions, robust Service Level Agreements (SLAs), on-site maintenance, and hybrid-cloud management software.

• Cash Flow Conversion: Dell converted operational execution into $8.15 billion in adjusted free cash flow during the quarter, returning $4.3 billion to shareholders via dividends and share buybacks.

The Synthesis: The Tollbooth Flywheel

When synthesizing TECH, CAPITAL, and EXECUTION, Dell’s strategic positioning becomes clear: system integration acts as a self-reinforcing flywheel.

As silicon hits physical power and memory walls, precision engineering creates high barriers to entry. Turnkey enterprise deployments yield predictable, high-margin revenue streams, generating the operational cash flow needed to fund further R&D and scale supply-chain integration.

Strategic Takeaways for SVTrivo Readers

1. System Integration as a Tollbooth: As silicon complexity increases, system integration, thermal engineering, and memory management become critical deployment bottlenecks. OEMs with scale capture sustainable margins by delivering fully integrated architectures.

2. The Memory Wall Constraint: Demand for DRAM and NAND memory now directly dictates AI server shipment timelines. Investors monitoring the hardware supply chain must look beyond GPU production yields to track memory capacity constraints.

3. Enterprise Infrastructure Refresh: AI deployment is driving a broader hardware upgrade cycle across enterprise storage and networking, extending compute value across the entire data center stack.

Research published for SVTrivo under the core pillars: TECH, CAPITAL, EXECUTION.

Explore research on AI hardware architecture, semiconductor supply chains, and market execution at SVTrivo.com. New subscribers receive a 7-day free trial.

Silicon Valley Trivopaedia is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber.

Author animation, 24 Aug 2026. Copper loss versus an optical pulse — illustration only. Not a measurement, and not a reprint of the Nature figures.

This weekend in Washington, DC, I read the full Nature Electronics review on co-packaged optics — not the abstract. Kim et al., published 19 August 2026. The next day, SK hynix put up a newsroom piece that uses the same numbers and a different sentence.

The paper is a domain review. It does not say what SK will ship.

The newsroom is a translation: chips → systems, HBM → the rack, optics → the memory interface.

A six-chart walkthrough of the packaging argument:

Those charts, and the ones below, are reconstructions. They are not reprints of the Nature figures. SK’s official adapted diagrams live in the newsroom post.

1. Two documents, one weekend

The review does what a good review should do. It puts HPC/AI in a communication-limited regime. It walks the packaging ladder from 2D side-by-side to 2.5D interposers to 3D hybrid bonding to monolithic integration. It tables components and commercial platforms. It lists the unglamorous constraints: lasers, thermal drift, coupling, yield, the missing picojoules in SerDes and DSP.

Seunghoon Hong of SK hynix AI Infra is a corresponding author. That is affiliation and framing, not a product SKU.

The newsroom (20 August) keeps the metrics and changes the customer. HBM already fixed the bottleneck inside the accelerator package. Hyperscale clusters now stall on data movement between systems. CPO is framed as the way to extend HBM innovation to the system, not as a replacement for HBM. The long draw is optical connectivity to the memory interface — an XPU pool talking to a memory pool over a photonic interposer.

Kyusang Lee (UVA):

Even if computing chips become more powerful, overall system performance cannot improve unless data movement between chips keeps pace.

Seunghoon Hong (SK Hynix):

CPO integrates optical transceivers into the same package as the processor… This fundamentally changes how data moves through AI systems.

The review inventories a field. The newsroom tells you why a memory vendor signed the inventory.

SK newsroom: https://news.skhynix.com/en/cpo-in-nature-electronics/

SK X (official adapted figures):

2. The bandwidth wall — four rates, not three

The review’s scaling discussion is the only chart that matters, and it is easy to misread.

HBM is the layer that partially caught up inside the package. The rack did not. If you flatten 8.8× into “hardware is exploding,” the rest of the paper becomes a transceiver brochure.

SK’s official adapted chart drops the DRAM line and keeps three curves: models 8.8×, hardware 3.0×, interconnect 1.4×. Cleaner for a press post. Worse for the HBM argument. The 1.6× line is why “just stack more HBM” is not an interconnect strategy.

Copper’s side of the wall is not mysterious. RC delay, skin effect, and the DSP/FEC latency and power required to recover a rotten electrical eye. That is why “the optical modulator is 0.1 pJ/bit” never equals “the link is 0.1 pJ/bit.”

3. Three numbers that have to land together

The review’s system target, repeated in the newsroom:

• Bandwidth: >100 Tbps class per node

• Energy: <1 pJ/bit

• Latency: <10 ns chip-to-chip

Miss any one of them and AllReduce turns GPUs into expensive heaters.

Lee lists four reasons CPO can become infrastructure rather than a cable: bandwidth density, energy-distance, parallel fan-out, immunity to EMI. Fair. None of those four is a 2026 GPU-package shipping spec.

4. The roadmap is packaging

• 2D: PIC and EIC side by side. Cheap. Long electrical hop.

• 2.5D: where the industry actually is — silicon or glass interposer.

• 3D hybrid bonding: Cu–Cu, bump capacitance gone.

• Monolithic: best on a slide, meanest in a fab.

The platforms the review names — Broadcom-class fabrics, NVIDIA Spectrum-X / Quantum-X photonics — are switch and scale-out stories. Saying “CPO is the mandated standard this year” is newsroom temperature, not the shipping floor.

5. After planar CPO: volume, or skip SerDes

Two bets sit past the 2.5D interposer.

Volumetric photonic interposers — route in 3D so waveguides do not keep crossing on one plane.

Micro-LED arrays — wide, slow, massively parallel. Skip high-speed SerDes. Energy can approach ~1 pJ/bit. Reach is tens of meters, not campus single-mode.

Lee points at ultrathin photonic materials and µLED parallelism as the next cut. Consistent with the review. Not a module you can order against HBM4E.

6. What SK added that the review would not say as a headline

The review will discuss optics-centric fabrics and memory pooling. It will not print “SK hynix’s technology roadmap” on the title. The newsroom will.

Hong does not talk like a DRAM datasheet owner. He talks like someone whose job is to put memory inside the customer’s system architecture. Lee is explicit about the prize: optical links at the memory interface lift the pin and capacity cage around the compute die, and let several accelerators share a pool.

HBM stays the fastest tier.

The architecture around HBM gets larger.

CPO is how a memory company stays in the room after the stack-height fight is over.

That is a coherent strategy sentence. It is not a commercial roadmap — no cadence, no socket, no power envelope for optical HBM I/O.

https://news.skhynix.com/en/cpo-in-nature-electronics/

7. What I am not taking from either text

I am not taking:

• “Foundational standard by 2026” as an engineering fact.

• <1 pJ/bit as something you can buy for a GPU package this year.

• The newsroom pool diagram as a product.

What holds:

• Training FLOPs and link bandwidth are on different slopes.

• HBM closed one wall and revealed the next.

• The remaining energy is in the electrical tax around the optical device.

• Packaging integration, not a new III–V logo, is the near-term lever.

• A memory company co-signing a CPO review is a systems bid, not a transceiver bid.

Copper cannot carry 100 Tbps-class node fabrics inside a 30–100 kW rack without eating the power budget. That is physics, not a vendor slide.

Optics in the package is the response that actually changes the energy and the reach. How far that optics is allowed to travel — to the switch, to the GPU, to the memory stack — is the argument SK chose to make in public. How soon anyone ships it at <1 pJ/bit, at yield, next to a hot compute die, is still a packaging problem.

The review mapped the domain. The newsroom told you which sentence a memory company wants attached to it. Neither one is a product. The product, when it exists, will be a bond pitch, a thermal loop, and a pJ number that survives the rack.

Sources

1. Byungsoo Kim et al., “Co-packaged optics for high-performance computing and artificial intelligence,” Nature Electronics 9, 853–867 (2026). https://doi.org/10.1038/s41928-026-01681-6

2. SK hynix Newsroom, 20 Aug 2026. https://news.skhynix.com/en/cpo-in-nature-electronics/

3. Reconstructed figures from @SVTrivo X:

Originally published on X in May 2026. Updated and archived here as part of Silicon Valley Trivopaedia.

For years, leading AI companies focused primarily on software optimization. NVIDIA’s CUDA ecosystem, along with mature libraries like cuDNN, TensorRT, and NCCL, was so dominant that most organizations believed they could maintain a competitive edge through software alone. “Let NVIDIA handle the hardware; we’ll optimize on top of it” was the prevailing mindset.

That assumption began to break down around 2023–2024.

The explosion in model scale dramatically increased both training and inference costs. More importantly, inference — not training — became the dominant cost driver in real-world production systems. Software optimizations helped, but they eventually hit hard limits in memory bandwidth, data-movement overhead, and low-precision compute efficiency. These bottlenecks could no longer be fully solved at the software layer.

At the same time, NVIDIA’s supply constraints and premium pricing during the H100/H200 era created serious operational and financial pressure. Hyperscalers investing tens of billions of dollars in AI infrastructure started treating GPU cost and power consumption as core strategic risks, not just procurement issues.

Equally important was workload specialization. Meta’s recommendation systems, Google’s search and Gemini workloads, Amazon’s Bedrock services, and Tesla’s FSD training have very different computational characteristics than generic large language models. These workloads benefit from hardware tailored to specific patterns — massive KV-cache handling, sparse operations, aggressive low-precision formats — which general-purpose GPUs are not optimally designed for.

Advances in chiplet architecture, advanced packaging, and the maturity of TSMC’s 3nm process finally made it technically and economically viable for these companies to design their own silicon. The potential gains in power efficiency, silicon cost, and performance per dollar (often estimated at 30–50%+) became too significant to ignore.

As a result, several hyperscalers moved from “software on top of NVIDIA” to building custom ASICs purpose-built for their specific needs. Below is the state of the major efforts, originally written in mid-2026 and lightly updated after Hot Chips 2026.

1. Meta — MTIA Series: The Most Aggressive Multi-Generation Push

In March 2026, Meta announced four generations of its Meta Training and Inference Accelerator — MTIA 300, 400, 450, and 500 — developed with Broadcom on a chiplet-based approach.

• MTIA 300 is in production, optimized for ranking and recommendation training.

• MTIA 400 expands coverage to general GenAI workloads and supports large-scale 72-chip configurations. As of Hot Chips 2026 (late August), Meta presented MTIA 400 as the near-term workhorse, with rollout in 2026.

• MTIA 450 and 500 are heavily optimized for GenAI inference. The standout improvement is memory bandwidth: MTIA 450 targets 18.4 TB/s, while MTIA 500 targets 27.6 TB/s with up to 512 GB of HBM. That directly helps large-context inference and high batch-size serving by keeping more KV cache in fast memory.

Meta’s ability to stack four generations in a short window reflects both the urgency of GenAI inference demand and the advantages of its chiplet + Broadcom partnership. The chips are already running at scale for Facebook and Instagram recommendations as well as Llama inference, with plans to expand further into training. Mass deployment of 450/500 is still slated for 2027.

2. Microsoft — Maia 200: Focused on Inference Economics

Announced in January 2026, Maia 200 is Microsoft’s clearest statement yet on custom silicon. It is purpose-built for inference, specifically the economics of token generation.

Built on TSMC 3nm with native FP8/FP4 tensor cores, it features 216 GB of HBM3e at 7 TB/s plus a large on-chip SRAM pool. Microsoft has claimed meaningful advantages versus competing custom chips from Amazon and Google on certain inference workloads.

By August 2026, the story had moved from announcement to architecture disclosure and production use:

• Microsoft presented Maia 200 at Hot Chips 2026 (750W TDP class, ~10 PFLOPS FP4 in disclosed figures).

• An arXiv paper described it as a software-defined dataflow system.

• Microsoft’s own MAI models are being trained and served with co-design on Maia 200, and some Copilot traffic is already routing to first-party models running on this stack.

The chip is no longer a slide. It is inside Azure.

3. Amazon — Trainium3: The Most Production-Ready at Scale — and Still Buying NVIDIA

Trainium3, unveiled at re:Invent 2025 and now in broad production, remains one of the most mature custom AI chips in real-world use. Built on TSMC 3nm, it powers the Trn3 UltraServer, which can integrate up to 144 chips in a single system.

It delivers up to 4.4× higher performance and roughly 4× better performance per watt versus Trainium2, with strong support for MoE architectures and low-precision formats (MXFP8/MXFP4). Multiple Bedrock customers have reported cost reductions of up to 50% versus GPU-based alternatives. Amazon’s advantage is not just the die — it is the tightly integrated server + software system.

The August 2026 update matters: Amazon is not walking away from NVIDIA. AWS committed to another 2 million NVIDIA GPUs for 2027–2028 (Blackwell Ultra / Rubin / Rubin Ultra), on top of an earlier ~1 million commitment. Custom silicon is a cost-and-control weapon. It is not a full substitution strategy — at least not yet.

4. Google — Ironwood, Then TPU v8

Google’s seventh-generation TPU, Ironwood, was designed for the “age of inference” while keeping strong training capability. It claimed up to 10× peak performance over TPU v5p and more than 4× per-chip improvement versus Trillium (v6e). Its distinctive strength is extreme scale: Superpods connecting thousands of chips, backed by Pathways.

By spring/summer 2026, Google had already moved to an eighth-generation split:

• TPU 8t for training

• TPU 8i for inference

Hot Chips 2026 made the systems-level ambition explicit: a ~9,600-chip training domain, dedicated inference silicon to avoid dark silicon, and continued co-design of networking + orchestration. Google’s bet is not “a faster chip.” It is treating tens or hundreds of thousands of chips as one coherent computer.

Ironwood is the previous chapter. TPU v8 is the current one.

5. Other Notable Efforts

Tesla Dojo. Continues to evolve for FSD training and large-scale internal AI workloads. Development on later Dojo generations resumed in 2026 after Tesla stabilized its AI5 path.

Apple Baltra. Working with Broadcom on a server-grade inference chip (2026–2027 window), chiplet design on TSMC 3nm, aimed at Apple Intelligence workloads.

OpenAI. The first custom chip, previously discussed as Project Titan, surfaced publicly as Jalapeño (with Broadcom). Engineering samples were running in 2026; Hot Chips 2026 and OpenAI’s own disclosures claimed better throughput per kilowatt and lower token latency than NVIDIA GB200/GB300-class systems on selected public inference benchmarks. Initial deployment is targeted for later 2026, with next generations already in design. This is the most important update since the original May post.

Broadcom. Still the critical enabler — design and supply partner for Meta, OpenAI, and others. Custom AI accelerator revenue has become a core growth engine, not a side business.

6. Key Takeaways

The shift toward custom ASICs is not merely about raw performance. It reflects a recognition that software optimization alone has hit diminishing returns against fundamental hardware constraints—especially memory bandwidth, power efficiency, and workload-specific compute patterns.

Common technical themes:

• Chiplet architectures

• Aggressive HBM (HBM3e now, HBM4 incoming)

• Native low-precision formats (FP8, FP4, MXFP)

• TSMC 3nm as the common manufacturing substrate

• Differentiation at architecture and systems level (rack, fabric, compiler, serving stack)

For NVIDIA, this is a long-term structural challenge even while CUDA, CUDA-X, and broad applicability remain powerful moats. Amazon’s latest GPU order is the clearest proof that NVIDIA is not being replaced overnight. It is being complemented and selectively displaced where workloads are stable enough to justify a custom die.

For hyperscalers, custom silicon has moved from an interesting side project to a core strategic capability: control over cost, performance, power, and supply-chain risk.

The next 18–24 months will likely bring even more aggressive roadmaps and greater heterogeneity in AI infrastructure. Each major player is doubling down on hardware tailored to its own strengths. The industry is no longer one GPU architecture with many software stacks. It is becoming many architectures with competing full stacks.

References

• Meta. (March 11, 2026). Expanding Meta’s Custom Silicon to Power Our AI Workloads.

• ServeTheHome. (August 25, 2026). Meta’s MTIA Custom AI Silicon at Hot Chips 2026.

• Microsoft. (January 26, 2026). Maia 200: The AI accelerator built for inference.

• ServeTheHome. (August 25, 2026). Microsoft’s Maia 200 AI Accelerator at Hot Chips 2026.

• Hoefler et al. (August 2026). Maia 200: A Software Defined Dataflow System for Large-scale AI Acceleration. arXiv:2608.24664.

• AWS. (December 2025). Amazon EC2 Trn3 UltraServers. re:Invent 2025.

• TechCrunch / NVIDIA earnings week. (August 26, 2026). Amazon’s expanded NVIDIA GPU commitment.

• Google Cloud. Ironwood TPU materials (2025–2026) and TPU 8t / 8i technical deep dive (April 2026).

• ServeTheHome. (August 25, 2026). Google’s TPUv8s for Training and Inference at Hot Chips 2026.

• OpenAI. (June 24, 2026). OpenAI and Broadcom unveil LLM-optimized inference chip.

• OpenAI. (August 24–25, 2026). Jalapeño performance disclosures / Hot Chips coverage.

• Reuters / HPCwire. (March 11, 2026). Meta in-house AI chip coverage.

A shorter version of this essay first appeared as an [X Article](https://x.com/i/article/2092506475327303680) on August 26, 2026.

Only a few years ago, Nvidia’s GTC was mostly a conference for developers and researchers. Now ordinary investors and the broader public put it on their calendars. “GPU” followed the same path. What once belonged to gamers and specialists is now everyday language whenever people talk about AI.

Something similar is happening to Hot Chips. As recently as last year, it was still the kind of technical conference you followed mainly if you cared about the silicon itself—architecture and circuit talks, RISC-V, and, for people in the interconnect world, optics and co-packaged optics (CPO). A colleague who works on optics told me they went last year for CPO, not for the consumer-AI circus. This year the same conference suddenly draws not only engineers but also tech media and influencers. If GTC has become the public stage for AI chips, Hot Chips has become the design stage, now open to wider markets and audiences. That is part of why announcements like OpenAI’s Jalapeño benchmarks and Cerebras’s wafer-scale roadmap drew attention in the same week.

The underlying agenda did not appear overnight. Optics and CPO were already on the program because racks are running into power, reach, and bandwidth walls that a faster GPU alone does not solve. What changed is who now treats those talks as market news.

Saying that AI semiconductors are “hot” already feels dated. The more accurate statement is that AI chips have become industrial infrastructure. That infrastructure is not converging on a single chip, a single company, or a single architecture. If anything, the opposite is true. In the AI world, Nvidia GPUs are driving; complementary technologies that GPUs alone cannot fully explain are growing at the same time.

1. Why Nvidia Is Number One—and Why It Is Not Number One Everywhere

Nvidia’s lead is not accidental. GPUs are strong at massive parallel compute, proven on training workloads, and backed by a deep software ecosystem centered on CUDA. The silicon is not the only factor. Productivity across building and deploying models on top of it is high. So whenever the question arises—“Can this replace Nvidia?”—people instinctively use the GPU as the reference point.

A GPU is not optimal for every domain. Training and inference are different jobs. Large-scale training prioritizes huge matrix math and flexible programming. Inference prioritizes power, latency, cost per token, and how stably you can serve traffic. In agentic systems, where models are called repeatedly, that difference compounds. One slow response is rarely just one slow response.

That is why complementary approaches have been studied for years: heterogeneous CPU–GPU systems, NPUs tuned for low-power inference, LPUs specialized for language-model serving, TPUs optimized for tensor operations, and ASICs carved for a specific service path. The names differ; the direction does not. The goal is not to deny what GPUs do well. It is to cover the places where GPUs are relatively expensive or slow.

2. The Trap in “Is It Better Than Nvidia?”

Whenever a company announces new silicon, the first question is almost automatic: Is it better than Nvidia’s GPU? Can it replace Nvidia?

The real answer is both yes and no. On specific workloads, specialized chips clearly win—performance per watt, ultra-low latency, narrow operator patterns, deterministic execution. On generality, developer ecosystem, model coverage, large-scale training, and full-stack maturity, Nvidia’s moat is still thick.

The problem is that the question is too binary. Markets and media remain comfortable with a single-winner frame. Real systems are not. A strong specialized chip is often not a device that erases Nvidia. It is a device that fills a gap in the AI world Nvidia is driving. The competitive key is shifting from “who builds the stronger single chip” to “who binds different chips into one coherent system.”

That fusion is concrete:

• Which parts of a model run on GPU, and which on NPU, LPU, TPU, or ASIC

• Compilers and runtimes that place work without forcing every developer to micromanage hardware

• Memory and interconnects that move data as little—and as fast—as possible between chips

• Total cost of ownership that includes power, cooling, floor space, operations, and development speed, not just chip price

When those links break, the advantage of specialized silicon disappears quickly.

3. Cerebras: Not a Replacement—an Architecture That Fills the Speed Gap

In my complementary view, one of the cases I have emphasized most consistently—and for the longest time—is Cerebras. The core point I have repeated since before the IPO is simple:

Cerebras is not a GPU replacement. It is a complementary solution meant to work with GPUs.

GPUs excel at throughput but lag on per-user token speed. Cerebras fills that speed gap. Together, they can raise both speed and throughput. The point is not who beats whom. It is how the roles are split.

That claim comes from architecture. Cerebras’s essence is extreme data locality. A full 300 mm wafer is treated as essentially one giant chip, with hundreds of thousands to roughly 900,000 small cores and SRAM placed next to them. Model weights can stay resident in on-chip SRAM, sharply reducing the memory-wall tax and inter-chip communication overhead GPUs repeatedly pay. On WSE-3, aggregate on-chip SRAM bandwidth is described around 21 PB/s; on WSE-3 Turbo, roughly on the order of double that. That is a different order of magnitude from typical GPU–HBM paths.

Experienced chip designers often have the same first reaction: yield will be catastrophic; you cannot test something that big or survive that many defects. Then you look at the actual design—tiny identical cores, massive redundancy, a dynamic re-routing fabric that maps around defective regions. It is not SRAM dumped on a wafer. It is cores and memory treated as one unit, with system-level yield engineered in. What first looked insane starts to look structurally coherent.

The recent CS-4 pushes that philosophy to rack scale: wafer-scale engines on the Nexus platform, aimed at ultra-fast inference and hyperscale deployment. Vendor claims emphasize large gains in token generation speed and tokens per watt versus prior generations. More important is the design intent: disaggregated inference, with prefill on GPUs or other accelerators and decode on Cerebras. The collaboration with AMD Helios is a concrete example of that split.

The CS-6 roadmap shown at Hot Chips 2026 goes one step further: keep wafer-scale SRAM and compute-fabric locality, then add 3D-stacked DRAM through ultra-high-bandwidth vertical connections to break the capacity ceiling. SRAM is fast but area-hungry; capacity has always been the trade-off. CS-6 is an attempt to gain capacity without throwing away the locality that makes the architecture special. Whether it works at production economics remains to be proven. The direction, however, is consistent.

Cerebras’s own wording at Hot Chips is the key sentence: by integrating wafer-scale SRAM and compute with 3D-stacked DRAM through ultra-high-bandwidth connections, CS-6 is designed to expand memory capacity without sacrificing the locality that makes wafer-scale fast.

OpenAI’s moves fit the same frame. Jalapeño is a custom inference ASIC for scaling internal infrastructure and improving efficiency. Paths like /ultrafast lean on Cerebras’s hardware characteristics for ultra-low latency. Different roles, operated in parallel—not one killing the other, but segments inside a large inference market.

What Jalapeño Shows

On August 25, 2026, OpenAI published the first public benchmarks for Jalapeño, the inference chip co-developed with Broadcom, at Hot Chips.

On SemiAnalysis’s InferenceX suite, OpenAI reported roughly 1.5–1.9× more AI work per watt and 1.7–3.6× lower end-to-end latency versus Nvidia GB200/GB300 rack systems across models such as GPT-OSS 120B, DeepSeek R1, and Kimi K2.5. Jalapeño is a ~700W-class part, inference-only, with limited deployment targeted later this year and broader rollout in 2027. [TechCrunch]

Reading those numbers as the end of the Nvidia era is premature. Results shift with package TDP versus facility power. Nvidia’s next generation was not in the comparison. Jalapeño does not replace training. Still, the message is clear: when a model company designs silicon around its own inference path, it can attack gaps left by general-purpose GPU design.

The same day’s context also reconfirms that OpenAI is not putting all inference on one class of hardware. One path optimizes for scale and cost; another for extreme speed. While specialized-chip announcements are often consumed as winner-replacement stories, the field is already practicing role division.

Specialization Is Connection, Not Isolation

This is not only an OpenAI–Cerebras story. Google splits TPUs across training and inference and diversifies design partners beyond a single supplier. AWS Inferentia/Trainium, Microsoft Maia, and Meta MTIA follow the same logic: bake repeated service patterns into silicon and cut power and cost.

Nvidia is not blind to the shift. It has moved from selling GPUs alone toward CPU–GPU combinations, rack-scale systems, and stronger inference software. The CUDA lock-in remains powerful. But the meaning of that moat is changing. The fight is less “GPU versus anti-GPU” and more “how GPU-centered systems coexist with specialized accelerators.”

An Investment Stance for a Growing Pie

Market-share figures vary by research house. What does not vary much is that Nvidia remains the dominant data-center AI accelerator franchise, while custom ASICs and specialized inference are growing quickly. The substance is simple: this is not a market where Nvidia must die for others to live. Aggregate demand is rising fast enough for multiple designs to find room at once.

The AI-semiconductor investment direction I take is this: for now, the market looks complementary rather than winner-take-all, so I keep a larger core position in Nvidia and add holdings in the companies that cover the layers GPUs do not fully own. That is different from spraying capital across many names on the theory that someone will win eventually.

What “complementary” means in practice:

• Nvidia still leads in training, general-purpose stacks, and the software ecosystem.

• AMD is the other merchant-GPU and rack-scale path.

• Broadcom is the custom-ASIC design and implementation layer behind chips such as OpenAI’s Jalapeño and Google’s TPUs.

• Google runs a separate deployment path through its own TPUs and cloud.

• Cerebras covers the ultra-low-latency inference gap with wafer-scale architecture.

These companies take demand in different parts of the system more than they erase one another.

In the portfolio, Nvidia’s weight is still larger than the sum of the other related holdings. The judgment that Nvidia is the core axis has not changed. At the same time, exposure to the other companies that can lead different AI-chip axes—AMD, Broadcom, Google, Cerebras—is being increased as the technology and market expand. Relative to Cerebras, Nvidia has been on the order of about ten times; AMD and Google roughly similar to Cerebras; Broadcom closer to AMD plus Cerebras combined.

The exact numbers matter less than the allocation sense: do not chase a single flag, and do not lose the center.

This is not “anyone can win” diversification. It is a stance aligned with a pie that is growing complementarily for now. One company may announce a new chip today; another may claim supremacy a few days later. Inside that noise, training remains largely GPU-centered, inference is differentiating quickly, and software plus system integration either completes or offsets hardware advantages.

Whether to buy any specific stock is ultimately a personal judgment. The weights and direction above are **not a recommendation**—only one example of translating a “not a replacement war, but complementary pie expansion” view into capital allocation. In this phase, the better question is not “Does this chip kill Nvidia?” but “Which segment of the full system does this chip make cheaper and faster?” When those segments grow together for a while, keeping the core axis while scaling the others is a coherent response.

What to Watch Next

The next months and years will be an era of chip announcements and, at the same time, an era of orchestration. What matters more than who claims larger FLOPS is who splits prefill and decode cleanly, who moves KV cache less, and who actually runs services inside the physical limits of power and cooling. That GTC and Hot Chips have both grown is itself a signal that these competitive and design debates have moved beyond a narrow conference wall.

GPUs are already common knowledge. The next piece of common knowledge may be this: the end state of the AI semiconductor contest is less likely to be one company’s flag than many chips complementing one another inside a rack, a cloud, and a service path—GPUs holding the center of throughput, wafer-scale designs like Cerebras filling the speed gap, and custom ASICs such as Jalapeño and TPUs bending the cost curve for specific services.

The side that designs and operates that fusion best will hold the more durable advantage—longer than any single chip’s scoreboard. Translated into investment terms: for now, keep the core on that complementary growth, and keep building the satellite axes around it.

This was the launch note. Who I am, and what is free versus paid, now lives on the About page.

Subscribe now

I started SVTrivo with a simple premise: the most valuable insights in Silicon Valley rarely fit into a single tweet or a press release.

Instead of rewashing daily tech news, this publication serves as a permanent research vault. We focus purely on how technology, capital, and real-world execution clash to shape the next market cycles.

What You Actually Get

Forget surface-level commentary. Here is what shows up in your inbox:

• Tech & AI Infrastructure. We look past the immediate hype. That means tracking hyperscaler CAPEX, physical supply chain bottlenecks, and actual enterprise deployment.

• Capital & Valuation. Breaking down VC deal mechanics, private liquidity pressures, and assets that public markets are completely mispricing.

• Execution Playbooks. Real, tactical teardowns on how elite founders scale when the macro backdrop turns messy.

Membership Options

Free

• 1 or 2 long-form essays every month on major structural shifts across tech and finance.

Paid Member ($15/month or $150/year)

• Weekly Deep Dives: Rigorous, data-backed teardowns on key sectors and high-growth companies.

• Real-Time Commentary: Raw, immediate analysis published right after major earnings, policy shifts, or unexpected market moves.

• Full Archive Access: Complete access to every past model, framework, and deep dive.

• Subscriber Threads: Direct access to private Q&A threads and subscriber-only discussions.

About the Author

I’ve spent years tracking global tech dynamics—building frameworks alongside a community of over 14,000 founders, investors, and operators on X. SVTrivo is where those ongoing conversations turn into actionable, high-conviction research.

Filtering out the noise. Compounding the signal.

Subscribe today to get the next report delivered straight to your inbox.