A shorter version of this essay first appeared as an [X Article](https://x.com/i/article/2092506475327303680) on August 26, 2026.
Only a few years ago, Nvidia’s GTC was mostly a conference for developers and researchers. Now ordinary investors and the broader public put it on their calendars. “GPU” followed the same path. What once belonged to gamers and specialists is now everyday language whenever people talk about AI.
Something similar is happening to Hot Chips. As recently as last year, it was still the kind of technical conference you followed mainly if you cared about the silicon itself—architecture and circuit talks, RISC-V, and, for people in the interconnect world, optics and co-packaged optics (CPO). A colleague who works on optics told me they went last year for CPO, not for the consumer-AI circus. This year the same conference suddenly draws not only engineers but also tech media and influencers. If GTC has become the public stage for AI chips, Hot Chips has become the design stage, now open to wider markets and audiences. That is part of why announcements like OpenAI’s Jalapeño benchmarks and Cerebras’s wafer-scale roadmap drew attention in the same week.
The underlying agenda did not appear overnight. Optics and CPO were already on the program because racks are running into power, reach, and bandwidth walls that a faster GPU alone does not solve. What changed is who now treats those talks as market news.
Saying that AI semiconductors are “hot” already feels dated. The more accurate statement is that AI chips have become industrial infrastructure. That infrastructure is not converging on a single chip, a single company, or a single architecture. If anything, the opposite is true. In the AI world, Nvidia GPUs are driving; complementary technologies that GPUs alone cannot fully explain are growing at the same time.
1. Why Nvidia Is Number One—and Why It Is Not Number One Everywhere
Nvidia’s lead is not accidental. GPUs are strong at massive parallel compute, proven on training workloads, and backed by a deep software ecosystem centered on CUDA. The silicon is not the only factor. Productivity across building and deploying models on top of it is high. So whenever the question arises—“Can this replace Nvidia?”—people instinctively use the GPU as the reference point.
A GPU is not optimal for every domain. Training and inference are different jobs. Large-scale training prioritizes huge matrix math and flexible programming. Inference prioritizes power, latency, cost per token, and how stably you can serve traffic. In agentic systems, where models are called repeatedly, that difference compounds. One slow response is rarely just one slow response.
That is why complementary approaches have been studied for years: heterogeneous CPU–GPU systems, NPUs tuned for low-power inference, LPUs specialized for language-model serving, TPUs optimized for tensor operations, and ASICs carved for a specific service path. The names differ; the direction does not. The goal is not to deny what GPUs do well. It is to cover the places where GPUs are relatively expensive or slow.
2. The Trap in “Is It Better Than Nvidia?”
Whenever a company announces new silicon, the first question is almost automatic: Is it better than Nvidia’s GPU? Can it replace Nvidia?
The real answer is both yes and no. On specific workloads, specialized chips clearly win—performance per watt, ultra-low latency, narrow operator patterns, deterministic execution. On generality, developer ecosystem, model coverage, large-scale training, and full-stack maturity, Nvidia’s moat is still thick.
The problem is that the question is too binary. Markets and media remain comfortable with a single-winner frame. Real systems are not. A strong specialized chip is often not a device that erases Nvidia. It is a device that fills a gap in the AI world Nvidia is driving. The competitive key is shifting from “who builds the stronger single chip” to “who binds different chips into one coherent system.”
That fusion is concrete:
Which parts of a model run on GPU, and which on NPU, LPU, TPU, or ASIC
Compilers and runtimes that place work without forcing every developer to micromanage hardware
Memory and interconnects that move data as little—and as fast—as possible between chips
Total cost of ownership that includes power, cooling, floor space, operations, and development speed, not just chip price
When those links break, the advantage of specialized silicon disappears quickly.
3. Cerebras: Not a Replacement—an Architecture That Fills the Speed Gap
In my complementary view, one of the cases I have emphasized most consistently—and for the longest time—is Cerebras. The core point I have repeated since before the IPO is simple:
Cerebras is not a GPU replacement. It is a complementary solution meant to work with GPUs.
GPUs excel at throughput but lag on per-user token speed. Cerebras fills that speed gap. Together, they can raise both speed and throughput. The point is not who beats whom. It is how the roles are split.
That claim comes from architecture. Cerebras’s essence is extreme data locality. A full 300 mm wafer is treated as essentially one giant chip, with hundreds of thousands to roughly 900,000 small cores and SRAM placed next to them. Model weights can stay resident in on-chip SRAM, sharply reducing the memory-wall tax and inter-chip communication overhead GPUs repeatedly pay. On WSE-3, aggregate on-chip SRAM bandwidth is described around 21 PB/s; on WSE-3 Turbo, roughly on the order of double that. That is a different order of magnitude from typical GPU–HBM paths.
Experienced chip designers often have the same first reaction: yield will be catastrophic; you cannot test something that big or survive that many defects. Then you look at the actual design—tiny identical cores, massive redundancy, a dynamic re-routing fabric that maps around defective regions. It is not SRAM dumped on a wafer. It is cores and memory treated as one unit, with system-level yield engineered in. What first looked insane starts to look structurally coherent.
The recent CS-4 pushes that philosophy to rack scale: wafer-scale engines on the Nexus platform, aimed at ultra-fast inference and hyperscale deployment. Vendor claims emphasize large gains in token generation speed and tokens per watt versus prior generations. More important is the design intent: disaggregated inference, with prefill on GPUs or other accelerators and decode on Cerebras. The collaboration with AMD Helios is a concrete example of that split.
The CS-6 roadmap shown at Hot Chips 2026 goes one step further: keep wafer-scale SRAM and compute-fabric locality, then add 3D-stacked DRAM through ultra-high-bandwidth vertical connections to break the capacity ceiling. SRAM is fast but area-hungry; capacity has always been the trade-off. CS-6 is an attempt to gain capacity without throwing away the locality that makes the architecture special. Whether it works at production economics remains to be proven. The direction, however, is consistent.
Cerebras’s own wording at Hot Chips is the key sentence: by integrating wafer-scale SRAM and compute with 3D-stacked DRAM through ultra-high-bandwidth connections, CS-6 is designed to expand memory capacity without sacrificing the locality that makes wafer-scale fast.
OpenAI’s moves fit the same frame. Jalapeño is a custom inference ASIC for scaling internal infrastructure and improving efficiency. Paths like /ultrafast lean on Cerebras’s hardware characteristics for ultra-low latency. Different roles, operated in parallel—not one killing the other, but segments inside a large inference market.
What Jalapeño Shows
On August 25, 2026, OpenAI published the first public benchmarks for Jalapeño, the inference chip co-developed with Broadcom, at Hot Chips.
On SemiAnalysis’s InferenceX suite, OpenAI reported roughly 1.5–1.9× more AI work per watt and 1.7–3.6× lower end-to-end latency versus Nvidia GB200/GB300 rack systems across models such as GPT-OSS 120B, DeepSeek R1, and Kimi K2.5. Jalapeño is a ~700W-class part, inference-only, with limited deployment targeted later this year and broader rollout in 2027. [TechCrunch]
Reading those numbers as the end of the Nvidia era is premature. Results shift with package TDP versus facility power. Nvidia’s next generation was not in the comparison. Jalapeño does not replace training. Still, the message is clear: when a model company designs silicon around its own inference path, it can attack gaps left by general-purpose GPU design.
The same day’s context also reconfirms that OpenAI is not putting all inference on one class of hardware. One path optimizes for scale and cost; another for extreme speed. While specialized-chip announcements are often consumed as winner-replacement stories, the field is already practicing role division.
Specialization Is Connection, Not Isolation
This is not only an OpenAI–Cerebras story. Google splits TPUs across training and inference and diversifies design partners beyond a single supplier. AWS Inferentia/Trainium, Microsoft Maia, and Meta MTIA follow the same logic: bake repeated service patterns into silicon and cut power and cost.
Nvidia is not blind to the shift. It has moved from selling GPUs alone toward CPU–GPU combinations, rack-scale systems, and stronger inference software. The CUDA lock-in remains powerful. But the meaning of that moat is changing. The fight is less “GPU versus anti-GPU” and more “how GPU-centered systems coexist with specialized accelerators.”
An Investment Stance for a Growing Pie
Market-share figures vary by research house. What does not vary much is that Nvidia remains the dominant data-center AI accelerator franchise, while custom ASICs and specialized inference are growing quickly. The substance is simple: this is not a market where Nvidia must die for others to live. Aggregate demand is rising fast enough for multiple designs to find room at once.
The AI-semiconductor investment direction I take is this: for now, the market looks complementary rather than winner-take-all, so I keep a larger core position in Nvidia and add holdings in the companies that cover the layers GPUs do not fully own. That is different from spraying capital across many names on the theory that someone will win eventually.
What “complementary” means in practice:
Nvidia still leads in training, general-purpose stacks, and the software ecosystem.
AMD is the other merchant-GPU and rack-scale path.
Broadcom is the custom-ASIC design and implementation layer behind chips such as OpenAI’s Jalapeño and Google’s TPUs.
Google runs a separate deployment path through its own TPUs and cloud.
Cerebras covers the ultra-low-latency inference gap with wafer-scale architecture.
These companies take demand in different parts of the system more than they erase one another.
In the portfolio, Nvidia’s weight is still larger than the sum of the other related holdings. The judgment that Nvidia is the core axis has not changed. At the same time, exposure to the other companies that can lead different AI-chip axes—AMD, Broadcom, Google, Cerebras—is being increased as the technology and market expand. Relative to Cerebras, Nvidia has been on the order of about ten times; AMD and Google roughly similar to Cerebras; Broadcom closer to AMD plus Cerebras combined.
The exact numbers matter less than the allocation sense: do not chase a single flag, and do not lose the center.
This is not “anyone can win” diversification. It is a stance aligned with a pie that is growing complementarily for now. One company may announce a new chip today; another may claim supremacy a few days later. Inside that noise, training remains largely GPU-centered, inference is differentiating quickly, and software plus system integration either completes or offsets hardware advantages.
Whether to buy any specific stock is ultimately a personal judgment. The weights and direction above are **not a recommendation**—only one example of translating a “not a replacement war, but complementary pie expansion” view into capital allocation. In this phase, the better question is not “Does this chip kill Nvidia?” but “Which segment of the full system does this chip make cheaper and faster?” When those segments grow together for a while, keeping the core axis while scaling the others is a coherent response.
What to Watch Next
The next months and years will be an era of chip announcements and, at the same time, an era of orchestration. What matters more than who claims larger FLOPS is who splits prefill and decode cleanly, who moves KV cache less, and who actually runs services inside the physical limits of power and cooling. That GTC and Hot Chips have both grown is itself a signal that these competitive and design debates have moved beyond a narrow conference wall.
GPUs are already common knowledge. The next piece of common knowledge may be this: the end state of the AI semiconductor contest is less likely to be one company’s flag than many chips complementing one another inside a rack, a cloud, and a service path—GPUs holding the center of throughput, wafer-scale designs like Cerebras filling the speed gap, and custom ASICs such as Jalapeño and TPUs bending the cost curve for specific services.
The side that designs and operates that fusion best will hold the more durable advantage—longer than any single chip’s scoreboard. Translated into investment terms: for now, keep the core on that complementary growth, and keep building the satellite axes around it.